This invention relates to sidelobe cancellers for sensing systems such as radar and sonar, and more particularly to improved weight determination arrangements which reduce redundant processes and thereby allow higher operating speed, reduced or simplified weight determination hardware, or both.
FIG. 1 is a simplified block diagram of a radar system in accordance with the invention. In FIG. 1, a first or main antenna 10 is coupled by a diplexer 12 to a transmitter (TX) 14 and to a receiver 16. Main antenna 10 produces a receive “beam” designated as 18, which includes a main lobe 20, and also includes a plurality of sidelobes 22 by which energy may be received from directions other than the main lobe. Representative first and second ancillary or auxiliary antennas 24a . . . 24n are located near main antenna 10, and respond generally to signal from the direction of the main lobe and from other directions. Each auxiliary antenna 24a . . . 24n is coupled to an individual receiver, illustrated as receivers 28a . . . . 28m. The receivers amplify, frequency convert, and perform analog-to-digital conversion, and other known functions as may be required to produce signals representative of amplitude and phase. The received signals from main receiver 16 are coupled to a delay (D) 30, and to the noninverting (+) input port of a summing circuit 32. The received signals from receivers 28a . . . 28m are applied to input ports of finite impulse response (FIR) filters 34a . . . . 34p associated with the receivers.
The received signals from auxiliary receivers 28a . . . 28m of FIG. 1a are also applied over buses 29a . . . 29s to a plurality of delay lines illustrated as blocks 38a . . . 38r. Representative delay line 38a is illustrated in FIG. 1c, and uses a cascade of delay elements represented as shift registers (S) 138a, 138b, and 138c to produce four time-sequential samples of the received signals on output data paths a1, a2, a3, a4 of a of bus 39a for application to weighting signal generator 40 of FIG. 1a. Weighting signal generator 40 processes the a1 . . . a4 sequential signal samples from delay 38a, the u1 . . . u4 sequential signal samples from delay 38r, other sets of sequential signal samples from other ones of the delays 38 (not illustrated), and the single delayed main signal sample from delay 30, to produce intermediate weighting signals on data paths 36a . . . . 36g. The intermediate weighting signals on paths 36a . . . 36p are processed in processor 50 to form weighting coefficients. The weighting coefficients are applied over buses 35a . . . 35q to FIR filters 34a . . . 34p. FIR filters 34a . . . 34p filter the complex received signals received over paths 29a . . . 29s from receivers 28a . . . 28m under the control of weighting signals, received over buses 35a . . . . 35q from weighting signal processor 50. The FIR filters filter the auxiliary signals originating from auxiliary antennas 24a . . . 24n. The filtered auxiliary signals are applied from FIR filters 34a . . . 34p to a summing (Σ) circuit illustrated as a block 42. The summed, filtered auxiliary signals are applied from summing circuit 42 to the inverting (−) input of summing circuit 32, where they are subtracted from the main signal to produce on data path 52 the desired signal, which represents the main lobe signals in which the unwanted signals arriving from directions other than that of main lobe 20 as suppressed.
FIG. 1b illustrates details of representative FIR filter 34a of FIG. 1a. In FIG. 1b, each FIR filter includes a tapped delay line, multipliers and a summer which together provide frequency response shaping to improve cancellation performance. In FIG. 1b, a tapped delay 134 includes shift registers 110, 112 and 114, which delay the signal from receiver 28a of FIG. 1a. A set of four multipliers 120, 122, 124 and 126 is coupled to receive mutually delayed signal samples from delay line 134. Each multiplier receives an independent weighting coefficient over bus 36a from weighting signal processor 50. As a result, the same signal sample moves in sequence from multiplier to multiplier within FIR filter 34a of FIG. 1b. More specifically, each undelayed sample arriving on path 17 is applied to multiplier 120 or multiplication by a first weighting coefficient. At the next clock cycle, shift register 110 stores the sample and makes it available to multiplier 122, and a new sample arrives at the input of shift register 110 and is applied to multiplier 120. During succeeding clock cycles, the original sample moves from shift register to shift register within delay line 134, being applied in succession to input ports of multipliers 120, 122, 124 and 126, and being multiplied therein by one of the weighting coefficients. At any moment, the sum signal generated at the output of summing circuit 128 of FIG. 1b is the sum of a plurality of time-sequential samples of the received auxiliary signals, each multiplied by a different one of the weighting coefficients (although one or more of the weighting coefficients may happen to have the same value).
FIG. 2a is a simplified block diagram of a radar system similar to that of FIG. 1a, but in which simple multipliers are used instead of FIR filters. Elements of FIG. 2a corresponding to those of FIG. 1a are designated by the same reference numerals. In FIG. 2a, weighting signal generator 240 has fewer input ports than weighting signal generator 40 of FIG. 1a, and consequently has fewer levels of calculation, but is otherwise identical. The intermediate weighting signals produced by weighting signal generator 240 of FIG. 2c are applied over data paths 236a . . . 236q processor 50, which generates the desired weighting coefficients for application to multipliers 234a . . . 234p for multiplying the auxiliary received signals. The multiplied auxiliary received signals are applied to summing circuit 42, and the summed, weighted auxiliary signals are subtracted from the main signal in summing circuit 32.
FIG. 2b is a simplified block diagram of intermediate weighting signal generator 240 of FIG. 2a. Weight generator 240 of FIG. 2b is illustrated for the case in which a single input signal or vector x5 originating from main antenna 10 of FIG. 2b is received by way of receiver 16, together with four auxiliary signals x1, x2, x3 and x4 originating from auxiliary antennas 28a . . . 28m. The arrangement of FIG. 2b is similar to, but not identical with that described at Chapter 4 in the Doctoral Dissertation in Electrical Engineering entitled, “Time and Order Recursive Multichannel Adaptive Filtering Techniques,” by Stanley Man Fung Yuen, presented to the faculties of the University of Pennsylvania in 1988.
It should initially be noted that the structure of weighting signal generator 240 of FIG. 2b can be used to directly generate the desired main signal free of the signals from unwanted directions. This is accomplished by, in the structure of FIG. 2b, taking signal x5 to be the main signal, and x1–x4 to be the auxiliary signals. In the arrangement of FIG. 2b, the main signal x5 is ultimately decorrelated or orthogonalized with the x1, x2, x3 and x4 vectors. The x1, x2 . . . x5 signals are applied to a first row of processors including processors designated A and B, described further in relation to FIG. 2c. The outputs from Row 1 are residues q21 to q51, which are used as inputs to the next row of decorrelators. Each residue q represents an input vector x decorrelated or orthogonalized from one or more of the other vectors x. For example, q21 produced by B processor 2121,2 represents vector x2 decorrelated from vector x1. Similarly, residue q32 produced at the output of B processor 2122,3 represents vector x3 decorrelated from vectors x1 and x2. This iterative process continues until the last residue is obtained, which in this case is q54, which is the residue of the main signal vector X5 which has made orthogonal to the remainder of the input vectors x1 . . . . x4. Residue q54 is made available on a path 208 of FIG. 2a and may be directly applied to further processing and display devices (not illustrated) rather than the difference signal from data path 52.
For the simple, illustrative case of FIG. 2b, taking the desired signal from conductor 208 may be appropriate. However, as mentioned below, it may be desirable to use weighting signals generated as intermediate products in the structure of FIG. 2b to produce the weighting signals for multipliers 234a–234p of FIG. 2a. As part of their operation, each B processor produces an intermediate weighting coefficient lxy, where subscript x describes the row, and subscript y describes the column.
More particularly, in FIG. 2b, the x1 auxiliary signal is applied as an input to A processor 2101, and to an input port of each of B processors 2121,2, 2121,3, 2121,4 and 2121,5. Auxiliary signal x2 is applied to another input port of B processor 2121,2, auxiliary signal x3 is applied to another input port of B processor 2121,3, and auxiliary signal x4 is applied to another input port of B processor 2121,4. Main signal x5 is applied to another input port of B processor 2121,5. A processor 2101 and B processors 2121,2 . . . 2121,5 are included within a first row (Row 1) of generator 240. In Row 1, the processed output of A processor 2101, which is designated L1,1, is applied to further input ports of each of B processors 2121,2, 2121,3, 2121,4 and 2121,5 of Row 1. The B processors of Row 1 of FIG. 2a produce intermediate weighting coefficients l and residues q. The residue produced by main B processor 2121,5 is designated q51, which is applied to an input of a B processor 2122,5 of Row 2. Processor 2121,2 of Row 1 produces a residue designated q21 which is applied to the input of an A processor 2102 of Row 2, and to inputs of B processors 2122,3, 2122,4, 2122,5 of Row 2. The residue produced by Row 1 B processor 2121,3 is designated q31, which is applied to an input port of Row 2 B processor 2122,3. The output signal produced by Row 1 B processor 2121,4 is designated q41, and is applied to an input port of Row 2 B processor 2122,4.
In Row 2 of FIG. 2b, the output signal of A processor 2102, which is designated L2,2, is applied to input ports of B processors 2122,3, 2122,4, 2122,5. The Row 2 B processors 2122,3, 2122,4, and 2122,5 each produce a residue. These residues are designated q32, q42, and q52, respectively. In FIG. 2b, residue q32 produced by B processor 2122,3 of Row 2 is applied to the input port of A processor 2103 of Row 3, and to input ports of B processors 2123,4 and 2123,5 of Row 3. Residue q42 produced by B processor 2122,4 of Row 2 is applied to an input port of B processor 2123,4 of Row 3. Residue q52 produced by B processor 2122,5 of Row 2 is applied to an input port of B processor 2123,5 of Row 3. Also within Row 3, the output, designated L3,3 produced by A processor 2103 is applied to further input ports of B processors 2123,4 and 2123,5. B processors 2123,4 and 2123,5 of Row 3 produce residues q43 and q53, respectively.
The q43 residue produced by B processor 2123,4 of Row 3 of FIG. 2b is applied to the input port of A processor 2104 of Row 4, and to B processor 2124,5. The q53 residue produced by B processor 2123,5 of Row 3 is applied to another input of B processor 2124,5 of Row 4. Also in Row 4, the output signal, designated L4,4, of A processor 2104 is applied to an input port of B processor 2124,5. B processor 2124,5 produces the final desired residue q54, which is the residue of the main signal vector x5 which has been made orthogonal to the rest of the input vectors.
As so far described, the arrangement of FIG. 2b generates the desired orthogonalized main signal. When the process of cancellation must be applied to large numbers of range cells, the above-described method may not be efficient, and may introduce speed limitations.
An alternative method for using the structure of FIG. 2b in the radar system of FIG. 2a is to ignore the signal on data path 208, and use only a subset of the range cells to generate weighting signals in the arrangement of FIG. 2a, which are then applied to the multipliers of FIG. 2a for all range cells. To generate the weights in this manner, sets of intermediate weighting coefficients designated generally as 1 are derived from weighting signal generator 240 of FIG. 2b. An intermediate weighting coefficient designated 1xy is generated in each B processor during generation of the residues, where subscript x represents the row in which the B processor is located, and subscript y represents the column. These intermediate weighting coefficients are extracted in sets at each row of the structure of FIG. 2b, and are further processed in processor 50 to produce the weights which are applied to multipliers 234a . . . 234p of FIG. 2a. The processing required in processing block 50 of FIG. 2b to form the weighting coefficients from the intermediate weight coefficients for application to multipliers 234a . . . 234p is well known in the art and is described in, for example, the aforementioned Yuen dissertation. This technique uses some of the range cells to produce weighting coefficients which are applied to the signals of all the range cells, thereby reducing the amount of processing.
FIG. 2c illustrates details of the A and B processors of FIG. 2b. More particularly, for definiteness, FIG. 2c illustrates representative A processor 2101 of FIG. 2b, and B processor 2121,2.
In FIG. 2c, the x1 auxiliary signal is applied in batches to a first input port of a summing multiplier (XΣ) 222 of a processor 2101,1 and to a processing block 220 designated by an asterisk (*) for taking the complex conjugate of input signal x1. The complex conjugate is applied to a second input port of summing multiplier 222. Such processing circuits are well known in the art, and are described, for example, in U.S. Pat. No. 4,941,117 issued Jul. 10, 1990 in the name of Yuen. The output signal L1,1, produced by A processor 2101 of FIG. 2c is applied to an input port 233 of B processor 2121,2, together with the x1 auxiliary signal applied to input port 232 and the x2 auxiliary signal applied to input port 231.
In B processor 2121,2 of FIG. 2c, the x1 signal applied to input port 232 is applied to a delay circuit or buffer 240 and to a complex conjugate processor 238, which produces the complex conjugate of x1 and applies it to an input port of summing multiplier 258. The x2 auxiliary signal input is applied to an input of a delay or buffer circuit 244, and to a second input of summing multiplier 258. Summing multiplier 258 takes the sum of products, and applies the result to the input of a dividing (÷) circuit 246, where the signal from summing multiplier 258 is divided by the L1,1 signal applied to input port 233 of B processor 2121,2. The divided signal, designated l1,2 is applied to a multiplier 242, where it is multiplied by the delayed x1 signal from buffer 240, to produce a signal which is applied to the inverting (−n) input port of a summing circuit 248. The non-inverting input port of summing circuit 248 receives delayed x2 signal from buffer 244, and combines it with the output of multiplier 242 to produce at an output port 254 of B processor 2121,2 a residue signal q21 for application to other processors as described in conjunction with FIG. 2b. The divided signal l1,2 produced at the output of dividing circuit 246 is the desired intermediate weighting signal produced by B processor 2121,2. Each of the other B processors of Row 1 of weighting signal generator 240 of FIG. 2b produces its own intermediate weighting coefficient, and taken together, the four weighting coefficients l1,2, l1,3, l1,4 and l1,5 produced by the B processors of Row 1 constitute one set of intermediate weighting coefficients.
Similarly, the three intermediate weighting coefficients l2,y of Row 2 of FIG. 2b are extracted as one set, the two l3,y of Row 3 constitute one set, and the set of Row 4 includes the single intermediate weighting coefficient l4,5.
The system of FIGS. 2a, 2b and 2c produces both the desired orthogonalized residue signals q, and the intermediate weighting coefficients lx,y, which can also be used to produce weighting signals for generating orthogonalized signals. Thus, the arrangement produces more information than the minimum required to produce the desired result. It would be desirable to reduce the amount of processing to produce the desired weight signals.
A further inefficiency exists when the scheme of FIGS. 2b and 2c is used in an arrangement such as that of FIG. 1a. When used to process sets of auxiliary signals such as a1 . . . a4; . . . ;u1 . . . u4; of FIG. 1a, the processing arrangement of FIG. 2b treats all its inputs as independent, even though the signals of any set of inputs (e.g. a1 . . . a4) are merely mutually delayed from each other, as described below in conjunction with FIG. 5. Thus, in the context of FIG. 1a, a weighting signal generator 40 operating as described in conjunction with FIG. 2b performs more than the minimum amount of processing. In such a case, the input signals to weighting signal generator 240 of FIG. 2b may be processed to take advantage of the time relationship of the signals in the shift registers of the FIR filters.